verilog code for serial adder subtractor vhdl

I haven't tried to debug this, but I think it is a timing problem:At the very first rising clock edge, you define both the inputs to your adder and register the adder's outputs (which are X at this point, because its inputs weren't defined before).With the idea of storing the result at indexcounter - 1 you are on the right track however you need to take care that you never try to store the result in a non-existing register such as carry(-1) or tempsum(-1). I've tried to start storing the result at indexcounter - 1 since the index jumps to 1 on the first clock cycle, but then I get a fatal error in the simulation.I've been trying to solve this problem for a few hours now and can't seem to figure out how to do it, so could you please take a look and see what I can do to fix it? Would be very much appreciated!I do have signals for saturation and overflow that I am going to implement later on but they aren't really used at the moment so don't worry about them.The design shouldn't update the final result before the addition/subtraction is finished if you're wondering why I have done it the way I have. But I obviously encounter problems since I'm probably still thinking a bit too much software programming I guess.The problem I have is that the counter increases to 1 right away when it enters the process so that when I try to add the vectors a = 0101 0101 and b = 1010 1010 I get y = 1111 111X and the carrys = 0000 000X. The logic behind it is very easily understood, you just have a counter for the index and so on. I'm trying to implement a serial adder/subtractor in VHDL, I've done it the ripple carry way before but now I'm supposed to implement the same functionality by just using one full adder cell instead of N-amount of cells so I have to shift the bits from the vectors in to the full adder/subtractor and store the result in another vector which I just shift the index for as well.

Serial Adder With Accumulator Verilog Code Serial Adder With Accumulator Verilog Code.ALL entity SAVHDL is Port ( I: in stdlogicvector ( 15 downto 0 ) O: out stdlogicvector ( 7 downto 0 ) ci, ai, bi, co, so: out stdlogic CLK: in stdlogic Load: in stdlogic ) end SAVHDL architecture Behavioral of SAVHDL is signal ina, inb, oreg: stdlogicvector ( 7 downto 0 ) signal so, ci, co: stdlogic begin -rec ina process ( CLK ) begin if CLK 'event and CLK = '1' then if ( Load = '1' ) then ina.

Just drop in a comment in the comments section below.Library IEEE use IEEE.STDLOGIC1164. Simulation result Full Subtractor Behavioral-waveform RTL Schematic Full Subtractor Behavioral-RTLĪs always, if you have any queries, we would love to address them.

Port ( A : in STD_LOGIC_VECTOR (2 downto 0) Īrchitecture Behavioral of FULLSUBTRACTOR_BEHAVIORAL_SOURCE is VHDL code for full subtractor using behavioral method library IEEE Įntity FULLSUBTRACTOR_BEHAVIORAL_SOURCE is

Verilog code for serial adder subtractor vhdl